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WM8816 Stereo Digital Volume Control
Advanced Information, September 2000, Rev 1.1
DESCRIPTION
The WM8816 is a highly linear stereo volume control for audio systems. The design is based on resistor chains with external op-amps, which provides flexibility for the supply voltage, signal swing, noise floor and cost optimisation. The gain of each channel can be independently programmed from -111.5dB to +15.5dB through a digital serial control interface. Audible clicks on gain changes are eliminated by changing gains only when a zero crossing has been detected in the signal. The device also features peak level detection, which can be used for Automatic Gain Control. The WM8816 operates from a single +5V supply and accepts signal input levels up to 18V. The WM8816 is available in a 16-pin SOIC package. It is guaranteed over a temperature range of -40 to 85C.
FEATURES
* * * * * * * * Gain range from -111.5dB to +15.5dB 0.5dB Gain step size Total Harmonic Distortion 0.001% (100dB) typical Crosstalk -110dB typical Input signals up to 18V Zero Detection for Gain Changes Hardware and Software Mute Power On/Off Transient Suppression
APPLICATIONS
* * * * Audio Amplifiers Consumer Audio / Entertainment Systems Mixing Desks Audio Recording Equipment
BLOCK DIAGRAM
(3) LFO LIN (4)
(2) LMO LGND (5)
LEFT OUT
Zero Crossing Detector
Peak Level Detector
+
CSB (6) MUTEB (8) DATA (9) CCLK (10)
External Opamps Control WM8816
DAC
Zero Crossing Detector
Peak Level Detector
(15) RMO
+
RIGHT OUT
RGND (12)
-
(14) RFO RIN (13)
(1) AVDD
(16) AGND
(7) DVDD
(11) DGND
WOLFSON MICROELECTRONICS LTD
Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK Tel: +44 (0) 131 667 9386 Fax: +44 (0) 131 667 5176 Email: sales@wolfson.co.uk http://www.wolfson.co.uk
Advanced information data sheets contain preliminary data on new products in the pre-production phase of development. Supplementary data will be published at a later date.
2000 Wolfson Microelectronics Ltd.
WM8816 PIN CONFIGURATION ORDERING INFORMATION
DEVICE
AVDD LMO LFO LIN LGND CSB DVDD MUTEB 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 AGND RMO RFO RIN RGND DGND CCLK DATA
Advanced Information
TEMP. RANGE -40 to +85oC
PACKAGE 16-pin SOIC (plastic)
XWM8816EDW
PIN DESCRIPTION
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 NAME AVDD LMO LFO LIN LGND CSB DVDD MUTEB DATA CCLK DGND RGND RIN RFO RMO AGND TYPE Supply Analogue Output Analogue Input Analogue Input Analogue Input Digital Input Supply Digital Input Digital In / Out Digital Input Supply Analogue Input Analogue Input Analogue Input Analogue Output Supply DESCRIPTION Supply Voltage for Analogue Circuitry External Op-amp Inverting Input (Left Channel) External Op-amp Feedback Signal (Left Channel) Input Signal (Left Channel) Input Signal Ground (Left Channel) Chip Select (active low) Supply Voltage for Digital Circuitry Mute (active low) Serial Interface Data Input / Output (tri-state) Serial Interface Clock Digital Ground Input Signal Ground (Right Channel) Input Signal (Right Channel) External Op-amp Feedback Signal (Right Channel) External Op-amp Inverting Input (Right Channel) Analogue Ground
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Advanced Information
WM8816
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore susceptible to damage from excessive static voltages. To optimise the distortion and noise performance of pins 3, 4, 13 and 14, the on-chip ESD protection circuitry has been restricted, and consequently only achieves 300V when characterised to the Human Body Model. Proper ESD precautions must be taken during handling and storage of this device. As per JEDEC specification JESD22-A112-A, this product requires specific storage conditions prior to surface mount assembly. It has been classified as having a Moisture Sensitivity Level of 3 and is therefore supplied in vacuum-sealed moisture barrier bags. CONDITION Input signal voltage Positive supply voltage (AVDD to AGND, DVDD to DGND) Input voltage (all other pins) Operating temperature Storage temperature MIN -20V -0.5V -0.5V -40C -55C MAX +20V 6V AVDD + 0.5V 85C 125C
RECOMMENDED OPERATING CONDITIONS
PARAMETER Input signal voltage Positive supply voltage Negative supply voltage Input signal grounds Operating temperature AVDD, DVDD AGND, DGND LGND, RGND -20 SYMBOL TEST CONDITIONS MIN -18 4.5 5 0 0 60 60 TYP MAX +18 5.5 UNIT V V V V C
ELECTRICAL CHARACTERISTICS
TEST CONDITIONS AVDD = 5.0V, AGND = 0V, TA = 25C, unless otherwise stated. PARAMETER Analogue Inputs / Outputs Input resistance Input capacitance Input offset voltage Supply current Power supply rejection ratio (Note 1) Gain Control Gain range Gain step size Gain error (Note 1) G D DE Lowest gains guaranteed by design, not tested in production. Between channels 113 -111.5 0.5 0.5 +15.5 dB dB dB RIN CIN Voffset IDD PSRR For any gain For any gain External OP275 opamp, gain = 1 From AVDD / AGND From AVDD 2.5 80 7 10 2 1 5 k pF mV mA dB SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
Gain match error (Note 1) Mute attenuation
ME MATT
0.2
dB dB
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WM8816
TEST CONDITIONS AVDD = 5.0V, AGND = 0V, TA = 25C, unless otherwise stated. PARAMETER Audio Performance Noise (Note 1) VIN = 0V, VOUT with OP275, A-weighed Total Harmonic Distortion plus Noise Dynamic Range (Note 1) Crosstalk (Note 1) Digital Inputs / Outputs Input low voltage Input high voltage Output low voltage Output high voltage Control Interface Timing Clock Frequency Period of CCLK high Period of CCLK low Rise time of CCLK Fall time of CCLK Hold time, CCLK high to CSB low Setup time, CSB low to CCLK high Setup time, valid DATA to CCLK high Hold time, CCLK high to invalid DATA Setup time, CCLK low to valid DATA Hold time, CSB high or 16th CCLK low to invalid DATA Hold time, 16th CCLK high to CSB high Setup time, CSB high to CCLK high Note: 1. Guaranteed by design. fCCLK tWHC tWLC tRC tFC tHCHS tSSLCH tSDCH tHCHD tDCLD tDSZ tHLCHS tSSHCH Load = 100pF Load = 3.3k 20 200 200 VIH to VIH VIL to VIL VIL to VIH VIH to VIL 20 100 100 100 500 500 VIL VIH VOL VOH All digital inputs All digital inputs ILoad = 2mA ILoad = 2mA DVDD -0.4 0.7 DVDD Gain = 0dB N Gain = -60dB Gain = mute THD+N DR CR Between channels, gain=0dB, fIN=1kHz VIN= 1Vrms, gain=0dB, VOUT with OP275, DC to 20 kHz 120 -100 4 2.5 0.001 (100) 130 -110 SYMBOL TEST CONDITIONS MIN TYP
Advanced Information
MAX 13
UNIT
V rms
% (dB) dB dB
0.3 DVDD 0.4
V V V V
1
MHz ns ns
100 100
ns ns ns ns ns ns
200 200
ns ns ns ns
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Advanced Information
WM8816
CONTROL INTERFACE TIMING DIAGRAM
tWLC CCLK tHCSH tSSLCH CSB tSDCH tHCHD DATA (IN) A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 tDCLD DATA (OUT) ADDRESS BYTE D7 D6 D5 D4 D3 D2 D1 D3 D2 D1 D0 tDSZ D0 tHLCHS tDSSHCH tWHC tRC tFC
DATA BYTE
Figure 1 Control Interface Timing Diagram
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WM8816 DEVICE DESCRIPTION
Advanced Information
The WM8816 is a stereo digital volume control designed for audio systems. The levels of the left and right analogue channels can be programmed independently through the serial interface. The resistor values in the internal resistor chains are decoded to 0.5 dB resolution with multiplexers, giving a gain range of -111.5 to +15.5 dB. The code for -112 dB activates mute for maximum attenuation. The WM8816 has two constant impedance signal inputs. The left channel input is between LIN and LGND, and the right channel between RIN and RGND. The output pins LFO, LMO (left) and RFO, RMO (right) are designed to interface directly to two external op-amps, which produce the volume controlled output signals. This provides flexibility for the supply voltage and signal swing; while the WM8816 runs at 5V, the output signal swing depends solely on the op-amp supply.
INTERFACES
Control information is written into or read back from the internal register via the serial control port. This port consists of a bi-directional data pin (DATA), an active low chip select pin (CSB) and the control clock (CCLK). Control data is shifted into the serial input register on the rising edges of CCLK pulses, while CSB is low. All control instructions require two bytes of data. The first byte contains a 4bit register address and a read/write bit, and the second byte is the control word. CSB must return to high at the end of each word. When reading from the control registers, data is shifted out on the falling edges of CCLK. When CSB is high, the DATA pin is in a high impedance state. In a multi-channel system, the same DATA and CCLK lines can thus be connected to several WM8816 volume controllers, and each device can be independently addressed by pulling its CSB pin low.
OPERATING MODES
When power is first applied, a power-on reset initialises the control registers mutes the WM8816. To activate the device, the MUTEB pin must be high and a non-zero value must be written to the gain register. After that the device can be muted again either by pulling the MUTEB pin low or by writing zero (00hex) to the gain register. For device testing, the MUTEB pin becomes an output when Bit 1 of the test register is high. Internal signals can then be directed to MUTEB and monitored.
CHANGING THE GAIN OF THE CHANNEL
The WM8816 has two gain registers for the left and right channels respectively. There is also an alias register address to update both gain registers simultaneously. When a new gain value is written into a gain register the WM8816 will wait until the next falling edge zero crossing in the input signal before changing the gain. This ensures that no audible click is produced at the output. If there are no zero crossings in the signal after 18ms, the gain is changed regardless. If both gain registers are changed simultaneously, the gain is changed first on the right and then the left channel.
PEAK LEVEL DETECTION
The WM8816 has an on-chip 8-bit digital-to-analogue converter (DAC) used for monitoring the peak level of the output signal. The DAC input value is programmed via the serial interface. The reference value VREF is calculated from VREF = k/256 x 18V, where k is the DAC input code. When a positive peak signal level exceeds this value, the peak detector sets Bit 1 (for the left channel) or Bit 0 (right channel) of the status register. These bits remain set until the status register is read.
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Advanced Information
WM8816
REGISTER MAP
REGISTER 7 Peak Detector Status CR4 X 6 1 ADDRESS BYTE BITS 5 0 4 1 3 1 2 R/W 1 X 0 X MSB...LSB Output code 00000000 00000001 00000010 00000011 Input code 11111111 11111110 11111101 : 00000010 00000001 00000000 Input code 11111111 11111110 11111101 : 11100000 00000010 00000001 00000000 Input code 11111111 11111110 11111101 : 11100000 00000010 00000001 00000000 Reserved Write to both gain registers DATA BYTE Function No overload Right overload Left overload Both overload DAC output 255/256 x 18V 254/256 x 18V 253/256 x 18V : 2/256 x 18V 1/256 x 18V AGND Gain dB +15.5 +15.0 +14.5 : 0.0 -111.0 -111.5 mute Gain dB +15.5 +15.0 +14.5 : 0.0 -111.0 -111.5 mute
Peak Detector Reference CR3
X
1
1
0
0
R/W
X
X
Left Channel Gain CR2
X
1
1
0
1
R/W
X
X
Right Channel Gain CR1
X
1
1
1
0
R/W
X
X
Test, CR5 Both Channel Gains
X X
1 1
1 0
1 0
1 1
R/W W
X X
X X
Table 1 Register Map Description Notes: 1. 2. 3. Address bit 2 is the read / write bit (1 for read, 0 for write). X are don't cares, set to 1 for minimum power consumption. All registers are set to their default value (all zeros) during power-on reset, except CR3 which is set to 255.
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WM8816
TEST REGISTER
Advanced Information
When bit 1 in register CR5 is set, MUTEB becomes an output pin. Bits 2, 3 and 4 select different internal signals which can then be seen via the MUTEB pin. CONDITION 7 Normal (MUTEB configured as input) 0 0 0 Test Mode (MUTEB configured as output) 0 0 0 0 0 0 6 0 0 0 0 0 0 0 0 0 DATA BYTE BITS 5 0 0 0 0 0 0 0 0 0 4 0 0 0 0 0 1 1 1 1 3 0 0 0 1 1 0 0 1 1 2 0 0 1 0 1 0 1 0 1 1 0 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 Latch the new gain value to resistor network Left delay generator Left peak detector Left zero crossing Left enable for zero crossing and delay generator Right delay generator Right peak detector Right zero crossing Right enable for zero crossing and delay generator FUNCTION
Table 2 Test Register Description
PERFORMANCE GRAPHS
-70
-80
-90 THD+N (dB) -100
-110
-120 -60
-50
-40
-30
-20
-10
+0
+10
Input Signal Level (dBV)
Figure 2 THD + Noise versus input level at gains of +6dB, 0dB, -6dB, -12dB and mute
+0 -20 -40 d B V -60 -80 -100 -120 -140
5k
10k
15k
20k
25k
30k
Frequency (Hz)
Figure 3 FFT of output signal with 1kHz, 1V rms sine wave input WOLFSON MICROELECTRONICS LTD
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Advanced Information
WM8816
+0 -20 -40 d B V -60 -80 -100 -120 -140 5k 10k 15k 20k 25k 30k Frequency (Hz)
Figure 4 FFT of output signal with 10kHz, 1V rms sine wave input
POWER SUPPLY DECOUPLING
For best audio performance, all digital activities should be avoided during analogue signal processing. Special attention should be paid to power and ground decoupling. If possible separate analogue and digital power supplies should be used. A clean analogue power supply should be used for AVDD. DVDD should be the same as AVDD to avoid latch-up phenomena. Decoupling capacitors should be located as close to the WM8816 as possible.
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WM8816 RECOMMENDED EXTERNAL COMPONENTS
Advanced Information
LFO 3 4 LIN LMO 2 5 LGND -18V + +18V
LEFT CHANNEL INPUT
RFO 14 13 RIN RMO 15 12 RGND -18V + +18V
RIGHT CHANNEL INPUT
WM8816
6 9 10 8 CSB DATA CCLK MUTEB AVDD AGND DVDD DGND 1 16 7 11 C2 C1
+5V DC
Micro Controller
+
C3
Note: Connect signal ground and non-inverting opamp input together on the PCB
Figure 5 Typical Application
RECOMMENDED EXTERNAL COMPONENTS VALUES
COMPONENT REFERENCE C1 C2 C3 SUGGESTED VALUE 220nF 220nF 10F DESCRIPTION Analogue Supply Decoupling Digital Supply Decoupling General Supply Decoupling
Table 3 Recommended External Components Values
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Advanced Information
WM8816
LFO 3 4 LIN LMO 2 5 + LGND +18V 2K 2K
DAC Balanced Output
WM8816
RFO 14
+18V -18V +18V + 2K + -18V
13
RIN RMO 15
12 RGND
-18V
2K
Figure 6 Configuration for Double Balanced Output (One Channel)
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WM8816 PACKAGE DIMENSIONS
DW: 16 PIN SOICW 7.5mm (0.3") Wide Body, 1.27mm Lead Pitch
Advanced Information
DM019.A
e
B
16
9
E
H
L
1 8
D
h x 45o
A1 -CA
SEATING PLANE
C
0.10 (0.004)
Symbols A A1 B C D e E h H L REF:
Dimensions (mm) MIN MAX 2.35 2.65 0.10 0.30 0.33 0.51 0.23 0.32 10.10 10.50 1.27 BSC 7.40 7.60 0.25 0.75 10.00 10.65 0.40 1.27 o o 0 8
Dimensions (Inches) MIN MAX 0.0926 0.1043 0.0040 0.0118 0.0130 0.0200 0.0091 0.0125 0.3465 0.3622 0.0500 BSC 0.2914 0.2992 0.0100 0.0290 0.3940 0.4190 0.0160 0.0500 o o 0 8
JEDEC.95, MS-013
NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS (INCHES). B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM (0.010IN). D. MEETS JEDEC.95 MS-013, VARIATION = AA. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
WOLFSON MICROELECTRONICS LTD
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